作者：徐欣, 周舟, 李楠, 孙兆林

作者单位：国防科技大学电子科学与工程学院, 湖南长沙 410073

关键词：高速海量数据缓存; FIFO存储器; DDR2 SDRAM技术; FPGA技术; 分时复用

摘要：

为了解决高速实时系统中海量数据的缓存问题,提出了一种基于DDR2 SDRAM的高速大容量异步FIFO设计方案。首先介绍了DDR2 SDRAM控制器和片上FIFO的原理与实现方法,基于DDR2 SDRAM的高带宽和分时复用技术设计了FIFO控制器的工作机制,最后深入分析了FIFO控制器各部分的工作原理并对其进行了实验。经过测试,基于DDR2 SDRAM的FIFO实现了最高475 MHz的总线速率,8~256位的总线位宽,2GB最大数据容量。该FIFO可以解决高速海量数据缓存的问题,在工程应用中有显著的参考价值。

Design and realization of high speed and deep asynchronous FIFO based on DDR2 SDRAM

XU Xin, ZHOU Zhou, LI Nan, SUN Zhao-lin

College of Electronic Science and Engineering, National University of Defense and Technology, Changsha 410073, China

Abstract: For solving the problem of high-speed mass data buffering, a new design has been proposed for high-speed and deep FIFO based on DDR2 SDRAM.Firstly, the principles and realization of DDR2 SDRAM controller and FIFO on chip were introduced.Then the mechanism of the FIFO controller has been designed based on the high bandwidth of DDR2 SDRAM and time-sharing technique.Finally, the principles of the FIFO controller have been deeply analyzed and implemented.Through stimulation and verification, the FIFO based on DDR2 SDRAM reaches the maximal bus rate of 475M, bus width from 8 to 256, and maximal capacity of 2GB.This kind of FIFO can satisfy the demands of high-speed mass data buffering, with brilliant future.

Keywords: High-speed mass data buffering; FIFO; DDR2 SDRAM; FPGA; Time-sharing

2009, 35(6): 34-37  收稿日期: 2009-6-21;收到修改稿日期: 2009-9-12

基金项目: 

作者简介: 徐欣(1975-),男,浙江缙云人,副教授,主要从事嵌入式技术、高速数据采集研究。

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