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摘要:
存储器进行内建自测试(Mernory built-in self-test, MBLST)时, 其功耗远远高于普通模式下的功耗, 致使电路易损坏并降低了芯片成品率。 针对上述问题, 提出了一种改进的线性反馈移位寄存器, 可在存储器内建自测试的地址序列生成过程中大幅降低翻转率。 首先基于优化的地址分割比生成两个优化的、 可逆的地址生成器, 随后利用时钟信号分别控制两个地址生成电路的时序关系, 最后对64 k×32 SRAM的MBIST的地址生成器进行了仿真验证。 结果表明, 改进的结构与传统的线性反馈移位寄存器(Linear feedback shift register, LFSR)的地址生成结构相比, 地址序列间的翻转率和动态功耗分别降低了71.1%和68.2%, 同时具有面积成本低、 速度快等特点。
Power consumption in test mode is much higher than that in normal mode, which is prone to causing circuit damage and reducing the yield of chips. To reduce the power dissipation efficiently, a modified linear feedback shift register (LFSR) is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test (MBIST). The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals. An address generator circuit for MBIST of 64 k×32 static random access memory (SRAM) is designed to illustrate the proposed scheme. Experimental results show that when the address bus size is 16 bits, compared with the traditional LFSR, the proposed LFSR can reduce the switching activity and dynamic power by 71.1% and 68.2%, respectively, with low area overhead.
关键词: 地址序列; 线性反馈移位寄存器; 存储器内建自测试; 地址生成器; 翻转率
作者: 虞致国,李青青,冯洋,顾晓峰,
作者单位: 江南大学电子工程系;江南大学物联网技术应用教育部工程研究中心;
刊名: 《测试科学与仪器》(英文)
Journal: Journal of Measurement Science and Instrumentation
年,卷(期): 2020, (3)
在线出版日期: 2020年09月28日
页数: 6
页码: 205-210